Patent · US Active

Method and apparatus of receive enable margining in memory interface

US12125518B2 · kind B2 · utility

0Cited by

5References

4Claims

0Family size

Assignee

SKYECHIP SDN BHD · MY

Inventors

Soon Chieh Lim · Merang, MY
Hoong Chin Ng · Merang, MY
Ching Liang Ooi · Bayan Lepas, MY
Chee Hak Teh · Kampung Bukit Kechil, MY

Key dates

Filing date	Apr 19, 2022
Grant date	Oct 22, 2024
Priority date	—
Expiry date	Dec 2, 2042

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present invention relates to a method and apparatus of calibrating memory interface, wherein said method and apparatus is able to periodically re-adjust the placement of the receive enable signal in order to have said receive enable signal to be in an optimum position in relation to the DQS signal from an external memory device to achieve maximum timing margin regardless of voltage or temperature drift and/or process aging to the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.