Apparatus and method for controlling gradual conductance change in synaptic element
US12125527B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jul 30, 2020 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jan 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a memory apparatus capable of causing a gradual resistance change for information processing in an analog manner to a synaptic element for implementing a neuromorphic system. To this end, the present invention provides a memory apparatus including: a memory array including a plurality of memory cells capable of selectively storing logic states and a plurality of bit lines and word lines connected to the plurality of memory cells; a controller for controlling a writing step and a reading step; a writing unit; and a reading unit, wherein the controller selects, in the writing step, one or more memory cells from among the plurality of memory cells through the writing unit, sequentially applies a writing voltage thereto to allow the logic states to be written therein, and applies, in the reading step, a reading voltage to the one or more memory cells, which are selected to have the logic states written therein, through the reading unit so as to determine synaptic weights through a sum of currents flowing through the one or more memory cells so that the selected one or more memory cells are allowed to be recognized to operate as one synaptic element.The pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.