Method for grinding wafer and wafer failure analysis method
US12125752B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 6, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | May 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for grinding the wafer includes: an initial wafer of which an edge has a test address is provided; a recombined water of which the test address is located in the middle is formed; a following circulation step is performed: a protective layer at least located above the test address is formed on an existing layer of the recombined water; the uncovered existing layer is grinded; the protective layer and the existing layer which is remaining are removed. It is determined whether the test address is exposed, if not, the next circulation step is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.