Method for fabricating electronic package structure
US12125760B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2023 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Feb 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an electronic package structure is disclosed. A solder mask layer is formed on an upper surface of a substrate. A recessed area is formed in the solder mask layer. An electronic component is mounted on the substrate. Pads are disposed on the upper surface of the substrate. The pads respectively correspond to the bumps on a first surface of the electronic component. The pads are electrically connected to the bumps. A heat treatment is performed to make the first surface close to the substrate and form a cavity in the recessed area. The cavity is between the first surface of the electronic component, the solder mask layer and the upper surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.