Environmentally protected photonic integrated circuit
US12125805B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Nov 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/3192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An environmentally protected photonic integrated circuit, PIC, including an indium phosphide-based substrate that is at least partially covered with an epitaxial semiconductor layer. The InP-based substrate and/or the epitaxial layer are covered with a layer stack comprising different non-semiconductor layers. At least a first layer of the layer stack is provided with a through-hole that is arranged at a predetermined location. The InP-based substrate or epitaxial layer being accessible via the through-hole. The PIC including a dielectric protective layer covering the layer stack thereby provides a mechanical coupling structure. The protective layer is configured to protect the PIC from environmental contaminants. An opto-electronic system including the PIC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.