Shuffler-free ADC error compensation
US12126351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jul 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.