Manufacturing method for capacitor structure, capacitor structure and memory
US12127415B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Jun 8, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jun 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
Abstract
A capacitor structure includes two electrodes arranged oppositely and a dielectric layer located between the two electrodes, wherein the dielectric layer includes at least two perovskite layers stacked; an amorphous layer is provided between every two adjacent perovskite layers; two outermost perovskite layers of the at least two perovskite layers are in contact with the two electrodes, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.