Hardware support for optimizing huge memory page selection
US12130750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2023 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Mar 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer systems often employ virtual address translation hierarchies in which virtual memory addresses are mapped to physical memory. Use of the virtual address translation hierarchy speeds up the virtual address translation when the required mapping is stored in one of the higher levels of the hierarchy. To reduce a number of misses occurring in the virtual address translation hierarchy, huge memory pages may be selectively employed, which map larger continuous regions of virtual memory to continuous regions of physical memory, thereby increasing the coverage of each entry in the virtual address translation hierarchy. The present disclosure provides hardware support for optimizing this huge memory page selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.