Method and memory controller for accessing multiple memories
US12131043B2 · kind B2 · utility
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Key dates
| Filing date | Jul 21, 2023 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Jul 21, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a memory controller for accessing a plurality of memories are provided. The method includes sorting a plurality of blocks of a plurality of memories to correspond to a plurality of disk logical addresses that are sequentially sorted. The plurality of blocks of the plurality of memories include M first blocks of a first memory and N second blocks of a second memory, where M and N are each an integer greater than 1, and the M first blocks of the first memory and the N second blocks of the second memory in the plurality of disk logical addresses are sorted in a non-sequential successive order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.