Trim/test interface for devices with low pin count or analog or no-connect pins
US12131799B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2023 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | May 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.