Transmission circuit, interface circuit, and memory
US12132018B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Dec 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1436
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transmission circuit includes: an upper-layer clock bonding pad configured to transmit a clock signal; M upper-layer data bonding pads configured to transmit data signals; a lower-layer clock bonding pad electrically connected with the upper-layer clock bonding pad, and an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; and M lower-layer data bonding pads electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, and an area of a lower-layer data bonding pad is smaller than that of an upper-layer data bonding pad. The upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.