Circuits for inverters and pull-up/pull-down circuits
US12132480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2023 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit is disclosed, comprising: an inverter comprising first and second inverter transistors, each having: a gate terminal connected in common to a drive node, a source terminal, connected to respective first and second voltage rails, and a drain terminal connected to a common first resistor, wherein an inverter output node is connected between the first resistor and the drain terminal of a shorting one of the transistors; a tying transistor connected between the drive node and the voltage rails to which the shorting transistor is connected; a biasing circuit connected to the tying transistor's control terminal and configured to be controlled by a local drive signal and bias the tying transistor control terminal to a voltage such that the tying transistor ties the drive node of the relevant voltage rail in response to the drive signal having a first state; and a circuit for providing the local drive signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.