Method and system for improving analog-to-digital conversion performance

US12132492B2 · kind B2 · utility

Assignee

• Hewlett Packard Enterprise Development LP · US

Inventors

• Dacheng Zhou · Fort Collins, US
• Peter Tsugio Kurahashi · Fort Collins, US
• Ryan Barnhill · Fort Collins, US
• Michael James Marshall · Fort Collins, US

Key dates

• Filing date: Dec 14, 2022
• Grant date: Oct 29, 2024
• Expiry date: Jun 22, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M1/38
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A frontend circuit of a time-interleaved ADC is provided. The frontend circuit can include a track-and-hold circuit to sample an analog input signal to the ADC, a sub-ADC circuit to convert the sampled analog input signal to a digital output signal, and a source-follower circuit. An input of the source-follower circuit can be coupled to an output of the track-and-hold circuit, and an output of the source-follower circuit can be coupled to an input of the sub-ADC circuit. The source-follower circuit is to provide buffering between the track-and-hold circuit and the sub-ADC circuit. The circuit further includes a common-mode-adjusting circuit to dynamically adjust common-mode settings of the time-interleaved ADC. While adjusting the common-mode settings, the common-mode-adjusting circuit can adjust, separately, an input common-mode voltage of the track-and-hold circuit and an input common-mode voltage of the sub-ADC circuit based on current Process, Voltage, and Temperature (PVT) conditions.