Patent · US Active

Data-dependent glitch and inter-symbol interference minimization in switched-capacitor circuits

US12132493B2 · kind B2 · utility

0Cited by

0References

18Claims

0Family size

Assignee

CIRRUS LOGIC, INC. · US

Inventors

Arashk NOROUZPOURSHIRAZI · Austin, US
Ramin Zanbaghi · Austin, US
Stephen T. Hodapp · Austin, US
Christophe J. Amadi · Austin, US
Ravi K. Kummaraguntla · Austin, US
Dhrubajyoti Dutta · Austin, US

Key dates

Filing date	Sep 26, 2022
Grant date	Oct 29, 2024
Priority date	—
Expiry date	Jan 31, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH03M3/464
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A system may include a sampling capacitor and a switch network. The switch network may include one or more first sampling switches electrically coupled to the sampling capacitor and configured to be activated during a first phase of a sampling cycle of the system and one or more second sampling switches electrically coupled to the sampling capacitor and configured to be activated during a second phase of the sampling cycle, wherein the switch network is configured to reset the sampling capacitor to a data-independent and/or signal-independent charge during a reset phase of the sampling cycle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.