Memory module, memory system, and operation method of memory controller
US12132501B2 · kind B2 · utility
0Cited by
6References
19Claims
0Family size
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Key dates
| Filing date | Aug 25, 2022 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Oct 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.