Self mixing frequency doubler tripler circuits for wireless communication
US12132512B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 1, 2022 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | Jun 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency tripler circuit includes an amplifier to receive a balanced input signal at an input frequency and outputs a balanced signal at a second harmonic of the input frequency. The frequency tripler circuit includes a passive double balanced mixer coupled to an output of the amplifier to receive the balanced signal at the second harmonic and the balanced input signal to generate an output balanced signal having a frequency triple the input frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.