Method and integrated circuit for clock recovery in an RFID tag
US12132816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2023 |
| Grant date | Oct 29, 2024 |
| Priority date | — |
| Expiry date | May 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
There is provided, a method for clock recovery in a RFID tag, the method includes receiving a RF field from a RFID reader. A field clock is generated from the received RF field, from which a clock recovery signal is generated. The RF field is modulated to produce a RF modulation. Generation of the clock recovery signal is paused while the RF field is being modulated. A modulation envelope signal is generated and used for load modulation. Generation of the clock recovery signal at the end of the RF modulation is resumed after a delay of one clock cycle from a falling edge of the modulation envelope signal. In another embodiment of the method, instead of adding the delay, a differential amplifier is used to increase RF field detection sensitivity. The method and the RFID tag ensures synchronized resumption of a PLL clock and the clock recovery signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.