Serial test circuit for controllable Chiplets

US12135354B1 · kind B1 · utility

Assignees

• NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS · CN
• NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD. · CN

Inventors

• Zhikuang Cai · 安丰镇, CN
• Yunbo Wang · Paris, FR
• Jian Song · 安丰镇, CN
• Guopeng Zhou · Shanghai, CN
• Jiafei Yao · 安丰镇, CN
• Binbin Xu · Xi'an, CN
• Henglu Wang · 安丰镇, CN
• Zixuan Wang · 安丰镇, CN
• Yufeng Guo · 安丰镇, CN

Key dates

• Filing date: Jun 20, 2022
• Grant date: Nov 5, 2024
• Expiry date: Jun 20, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318572
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Disclosed is a serial test circuit for controllable Chiplets, which belongs to the technical field of test or measurement of semiconductor devices during manufacturing or processing. The test circuit includes a master control test module, a slave control test module, a clock controlling module and an outputting module. The master control test module is composed of a test access port module, a segment insertion bit module and a test data register module. The test controlling signal is generated by the master control test module, and the test inputting signals of the slave Chiplets are respectively controlled by the slave control test module after receiving the test controlling signal. At the same time, the test controlling signal is inputted to the clock controlling module to obtain the clock signals of the slave Chiplets. The output signal of the test outputting module is determined by the test controlling signal.