Biasing control for compound semiconductors
US12135574B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2022 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | Aug 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/242
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A compound semiconductor integrated circuit is disclosed, which includes biasing circuitry for generating a bias voltage at a bias output node. The biasing circuitry comprises a first circuit branch configured to extend between a defined voltage and a supply voltage. The first circuit branch includes a first transistor configured as a current source to generate a defined current in the first circuit branch and a controllably variable resistance. The bias output node is coupled to the first circuit branch at a first node which is between the controllably variable resistance and the first transistor. The biasing circuitry is operable so that the resistance value of the controllably variable resistance varies with a control voltage so as to vary the value of the bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.