On-chip packet caching apparatus, method and computer-readable medium using idle address management module
US12135650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2021 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | Sep 7, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application provides an on-chip cache apparatus, an on-chip cache on-chip cache read-write method and a computer-readable medium, the on-chip cache apparatus includes: a read-write processing module, a cache module and a memory module; the read-write processing module is connected with the cache module and the memory module respectively, and is configured to store packets into the cache module and the memory module, read packets stored in the cache module and the memory module, and transfer packets cached in the cache module to the memory module for storing; the cache module is connected with the memory module through the read-write processing module, and includes at least one cache register configured to temporarily cache packets; and the memory module is connected with the read-write processing module, and is configured to store the packets cached in the cache module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.