Dynamic processor architecture control
US12135680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2018 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/44589
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprising a control unit and a plurality of processing units interacting according to an operating architecture imposed dynamically by the control unit from among at least two of the following architectures: a single instruction multiple data (SIMD) stream architecture, a multiple instruction single data (MISD) stream architecture, and a multiple instruction multiple data (MIMD) stream architecture. The operating architecture is imposed dynamically by the control unit according to: configuration functions included in a machine code, and/or data to be processed and current processing instructions received as input of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.