Disaggregated memory server having chassis with a plurality of receptacles accessible configured to convey data with PCIe bus and plurality of memory banks
US12135884B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Dec 21, 2022 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | Dec 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a disaggregated memory server, which in some examples is a rack-mounted hardware appliance comprising a pool of memory for allocation to memory clients. Examples of memory clients may include one or more rack-mounted computing devices co-located on a rack with the disaggregated memory server. The disaggregated memory server may be optimized for high-speed dynamic memory allocation to the other computing devices in the rack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.