Circuit and timer for memory
US12135902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2022 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | Jul 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/125
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Various examples may include an apparatus including a memory to store ingressing data or egressing data, a timer to generate a timing signal responsive to a user-configurable time interval, and a circuit to move the ingressing data or the egressing data from the memory at least partially responsive to the timing signal generated by the timer. Various examples may include a method including receiving a data packet at a network-facing interface, writing data of the data packet into a memory, receiving a timing signal, and responsive to the timing signal, providing the data from the memory at a device-facing interface. Various examples may include a method including receiving data at a device-facing interface, writing the data to a memory, receiving a timing signal, and responsive to the timing signal, providing a data packet including the data at a network-facing interface. Related devices, systems and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.