Fully self-aligned interconnect structure
US12136567B2 · kind B2 · utility
0Cited by
11References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 13, 2022 |
| Grant date | Nov 5, 2024 |
| Priority date | — |
| Expiry date | May 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.