Semiconductor memory device

US12137559B2 · kind B2 · utility

Assignee

• Kioxia Corporation · JP

Inventors

• Takuya Inatsuka · Yokkaichi, JP
• Tadashi Iguchi · Yokkaichi, JP
• Murato Kawai · Yokkaichi, JP
• Hisashi Kato · Tokyo, JP
• Megumi Ishiduki · Yokohama, JP

Key dates

• Filing date: Mar 14, 2023
• Grant date: Nov 5, 2024
• Expiry date: Mar 14, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/50

Abstract

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.