Memory control component with split auxiliary channel
US12141027B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 31, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Jan 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory control component allocates a portion of an auxiliary signaling channel and corresponding memory storage, conventionally dedicated to error correction code (ECC) conveyance and storage, for conveyance of metadata and/or other types of component-level information—splitting the auxiliary channel between metadata and ECC conveyance/storage in proportions that obviate conventional metadata conveyance/storage via the primary data channel and thus maintaining full primary channel bandwidth/storage-capacity for user data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.