Address translation prefetching for input/output devices
US12141075B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Jun 9, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Aug 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example of the present technology, an input/output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.