Providing communication between storage processors through an interconnect and a set of storage devices
US12141472B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jan 11, 2023 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Apr 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques provide communication between storage processors (SPs) of a storage array. The techniques involve electrically coupling the SPs with an interconnect of the storage array. The techniques further involve electrically coupling a storage device having dual on-device controllers with the interconnect. The techniques further involve establishing a communications pathway between the SPs through the interconnect and the storage device having the dual on-device controllers while the SPs are electrically coupled with the interconnect and while the storage device is electrically coupled with the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.