Memory device, memory module including the memory device, and operating method of memory controller
US12141478B2 · kind B2 · utility
0Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Sep 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.