Ultra low-power negative margin timing monitoring method for neural network circuit
US12141682B2 · kind B2 · utility
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Key dates
| Filing date | Feb 22, 2021 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Sep 16, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.