Cache architecture for image warp processing systems and methods
US12141893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T5/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device may include a display for displaying an image frame based on warped image data and image processing circuitry to generate the warped image data by warping input image data to account for one or more distortions associated with displaying the image. The image processing circuitry may include a two-stage cache architecture having an first cache and an second cache and warp the input image data by generating mapping data indicative of a warp between the input image space and the output image space and fetching the input image data to populate the first cache. Warping may also include populating the second cache with a grouping of pixel values from the first cache that are selected according to a sliding window that traverses the first cache based on the mapping data and interpolating between pixel values of the grouping to generate pixel values of the warped image data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.