Data delay cell for rise time programming in write preamplifier
US12142305B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2023 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Sep 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/022
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data delay circuit, for delaying a portion of a data signal for application to a write head of a hard disk drive, includes a data delay cell including two inverters and a charge current source for charging at least one of the inverters, and a bias circuit for programming delay of the data delay cell. The bias circuit is in current-mirroring relationship with the charge current source and includes a current-based digital-to-analog converter (DAC) for programmably selecting the delay of the data delay cell, and a reference current source for the DAC. The data delay cell and the bias circuit are subject to gain error, and the data delay circuit further includes compensation circuitry for reducing the effect of the gain error. The compensation circuitry may include replica charge current and reference current sources that are fed back through a gain cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.