Semiconductor device
US12142607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Jun 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes first and second active regions parallel to each other and respectively extending in a first direction, an isolation layer between the first and second active regions, a first line structure and a second line structure overlapping the first and second active regions and the isolation layer, parallel to each other, and extending in a second direction, a first source/drain region on the first active region, and a second source/drain region on the second active region. The first line structure includes a first gate structure, a second gate structure, and a first insulating separation pattern between the first and second gate structures. The second line structure includes a third gate structure, a fourth gate structure, and a second insulating separation pattern between the third and fourth gate structures. The first and second insulating separation patterns are spaced apart from each other. The first insulating separation pattern has first and second side surfaces opposing each other, and third and fourth side surfaces opposing each other. At least one of the first and second side surfaces and at least one of the third and fourth side surfaces have diff…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.