Device for correcting duty cycle and method for correcting duty cycle
US12143109B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2023 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Jun 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for correcting a duty cycle, comprising: a duty adjustor circuit, configured to receive an input clock signal and a tuning signal, to generate an output clock signal; a first charge pump, configured to charge a first capacitor for a predetermined time period to generate a first voltage; a second charge pump, configured to charge a second capacitor for a time period corresponding to the duty cycle of the output clock signal to generate a second voltage; a first sampling and hold circuit, configured to sample the first voltage to generate a first sampled voltage; a second sampling and hold circuit, configured to sample the second voltage to generate a second sampled voltage; and an error amplifier, configured to generate the tuning signal according to a difference value between the first sampled voltage and the second sampled voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.