Error tolerant communication circuit and error tolerant communication
US12143214B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2023 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Mar 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0055
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error tolerant communication circuit includes an acquisition part that acquires a packet, in packet communication in which data is divided into units of packets and transmitted, including a control flag for controlling the packet communication and a CRC code and received from an external device; a storage part that stores, in advance, an inspection packet including at least one of a packet including a control flag indicating an ACK acknowledgment and a CRC code corresponding to the ACK acknowledgment, and a packet including a control flag indicating a negative acknowledgment and a CRC code corresponding to the negative acknowledgment; and a detection part that compares the received packet and the inspection packet with each other and detects a bit error with respect to the received packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.