TFT panel and test method
US12146906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2019 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Oct 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2844
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A thin-film transistor (TFT) panel and a test method are disclosed. The TFT panel includes: m×n bonding pads, where m and n are both natural numbers greater than or equal to 1, and the m×n bonding pads are arranged correspondingly to and electrically connected to TFT units in a TFT active area; a TFT test area including m drive pads, n test pads, and m×n TFT devices, where the m×n TFT devices are divided into n groups, each of which includes m TFT devices. the m TFT devices in each group corresponding to and are electrically connected to the m drive pads and m bonding pads respectively, and the m TFT devices in each group are electrically connected to a same test pad of the n test pads. The m×n bonding pads that were originally bonded by pressure once are tested in m sessions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.