Segmented digital-to-time converter
US12147201B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Jan 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1974
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.