Memory controller prioritizing writing compressed data
US12147341B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2020 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Oct 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, method, and system provided herein are directed to prioritizing cache line writing of compressed data. The memory controller comprises a cache line compression engine that receives raw data, compresses the raw data, determines a compression rate between the raw data and the compressed data, determines whether the compression rate is greater than a predetermined rate, and outputs the compressed data as data-to-be-written if the compression rate is greater than the predetermined rate. In response to determining that the compression rate is greater than the predetermined rate, the cache line compression engine generates a compression signal indicating the data-to-be-written is the compressed data and sends the compression signal to a scheduler of a command queue in the memory controller where writing of compressed data is prioritized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.