Semiconductor memory device
US12148479B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2023 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Aug 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.