Semiconductor device
US12148701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2024 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Mar 4, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a metal pattern on a semiconductor substrate; an etch stop layer covering the metal pattern, the etch stop layer including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer; an interlayer dielectric layer on the etch stop layer; and a contact plug penetrating the interlayer dielectric layer and the etch stop layer, the contact plug being connected to the metal pattern, wherein the first insulation layer includes a first insulating material that contains a metallic element and nitrogen, wherein the second insulation layer includes a second insulating material that contains carbon, and wherein the third insulation layer includes a third insulating material that does not contain a metallic element and carbon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.