Homogeneous chiplets configurable as a two-dimensional system or a three-dimensional system
US12148707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | May 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1437
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first logic block and a first memory that are interconnected via a first path for transfer of data signals between the first logic block and the first memory block. A second HC including a second IC die having a second logic block and a second memory block, interconnected via a second path for transfer of data signals between the second logic block and the second memory block, is stacked vertically on top of the first HC to provide a third path for transfer of data signals between the first logic block and the second memory block and a fourth path for transfer of data signals between the second logic block and the first memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.