Array substrate and display panel
US12148762B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 26, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | May 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate and a display panel are provided. The array substrate includes a base substrate and a first conductive layer, a first insulating layer, a second conductive layer and a third conductive layer which are sequentially stacked on the base substrate, the first insulating layer insulates the first conductive layer from the second conductive layer, the first conductive layer includes a first signal line, the second conductive layer includes a second signal line and a first connection part spaced apart from each other, the third conductive layer includes a second connection part, the first connection part is electrically connected with the first signal line through a first via hole in the first insulating layer; the second connection part is electrically connected with the first connection part and the second signal line to constitute a connection structure electrically connecting the first signal line with the second signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.