Transconductor circuitry with adaptive biasing
US12149219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2019 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Jan 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45491
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transconductor circuitry (10) with adaptive biasing comprises a first input terminal (E10a) to apply a first input signal (inp), and a second input terminal (E10b) to apply a second input signal (inn). A control circuit (200) is configured to control a first controllable current source (110) in a first current path (101) and a second controllable current source (120) in a second current path (102) in response to at least one of a first potential of a first node (N1) of the first current path (101) and a second potential of a second node (N2) of the second current path (102). The first node (N1) is located between a first transistor (150) and the first controllable current source (110), and the second node (N2) is located between a second transistor (160) and the second controllable current source (120).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.