Pre-biased dual current sensing
US12149236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | May 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example, a system includes a first transistor and a second transistor, the first transistor and the second transistor configured to provide current to a load. The system also includes a sense transistor coupled to the first transistor, the sense transistor configured to sense a current flowing through the first transistor. The system includes an amplifier coupled to the sense transistor, where the amplifier includes a first input, a second input, and an output. The system also includes pre-bias circuitry coupled to the amplifier, where the pre-bias circuitry is configured to provide a voltage to the first input of the amplifier responsive to the first transistor being off, where the voltage biases the amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.