Frequency divider and memory device including the same
US12149247B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Sep 14, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Mar 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.