Single-cycle byte correcting and multi-byte detecting error code
US12149259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Sep 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1575
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.