Storing misaligned reference pixel tiles

US12149720B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Sriganesh BALAKUMAR · San Jose, US
• Kapil Garg · Fremont, US
• Gaurav Avinash Patil · San Jose, US
• Rajesh Chowdary Chitturi · San Jose, US
• Prasanth Gomatam · San Diego, US
• Sravan Kumar GOPANAPALLE · San Diego, US

Key dates

• Filing date: Jun 10, 2022
• Grant date: Nov 19, 2024
• Expiry date: Oct 20, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04N19/176
• WIPO field: Audio-visual technology
• WIPO sector: Electrical engineering

Abstract

Systems and techniques are provided for caching misaligned pixel tiles. A method includes determining a first codec region including a first region of a frame; determining whether pixels of a first version of a pixel tile were stored in a cache while coding blocks from a second codec region, the pixel tile corresponding to a location within the frame; based on whether the pixels were stored in the cache, determining whether to read the first version of the pixel tile from the cache or retrieve a second version of the pixel tile from a memory device, the second version of the pixel tile including pixels from the first codec region that are not in the first version of the pixel tile; and coding a block based on the first version of the pixel tile read from the cache or second version of the pixel tile retrieved from the memory device.