Method and procedure for miniaturing a multi-layer PCB
US12150237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Jun 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09854
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multiple layer printed circuit board including a plurality of layers, vertical interconnect accesses (VIAs), and a vertical interconnect access (VIA) bridge. The layers may include signal layers, prepreg substrate layers disposed between the signal layers, ground plane layers, wherein each of the ground plane layers abuts one of the prepreg substrate layers, inner signal layers, wherein each of the inner signal layers abuts one of the prepreg substrate layers, and a core substrate layer disposed between the signal layers, wherein two of the inner signal layers abut opposed sides of the core substrate layer. The VIAs extend through at least some of the layers, wherein each of the VIAs is formed by aligned apertures through adjoining ones of the prepreg substrate layers, ground plane layers, and inner signal layers. The VIA bridge is coupled to the VIAs to convey heat to a heat sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.