Memory device structure for reducing thermal crosstalk
US12150394B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 22, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Mar 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
The present disclosure is directed towards an integrated chip including a first memory cell overlying a substrate. The first memory cell comprises a first data storage layer. A second memory cell is adjacent to the first memory cell. A dielectric layer is disposed laterally between the first memory cell and the second memory cell. An air gap is disposed within the dielectric layer. The air gap is spaced laterally between the first memory cell and the second memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.