System and method to fix min-delay violation post fabrication
US12153086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2023 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jul 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method of testing an integrated circuit provide a first clock signal to a first flip-flop with an output to a functional circuit, provide a second clock signal to a second flip-flop with an input from the functional circuit, wherein the second flip-flip has a minimum hold time, provide a test input to the first flip-flop, observe a signal propagation time through the functional circuit, determine the signal propagation time is less than the minimum hold time of the second flip-flop, and increasing a timing separation by adding a unit of delay to the first clock signal or subtracting a unit of delay from the second clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.